Career Highlights

  • My research interests are oriented towards developing reliable digital integrated circuits. Particular emphasis in soft errors modeling and evaluation of their effect on complex integrated design and transient faults hardware/software tolerant design. I am also investigating aging induced reliability issues through modelling and mitigation of these effects cross abstraction layers. I am also involved in  defect and variation tolerance for emerging technologies.
  • My research activities have been supported by national funding such as French ANR, European funding such as EU projects (MEDEA, CATRENE, COST, RISE), and industrial support.
  • 5 book chapters, 13 journal papers, 13 invited conferences, more than 95 publications in international conferences
  • 4 best paper award et 1 outstanding paper award of prestigious conferences such as IEEE Design Automation and Test in Europe (in 2000 and 2015), IEEE Interenational Reliability and Physics of Semiconductors  (2012), IEEE VLSI Test Symposium (2004), IEEE Nanoarch (2016)
  • Since 2004 Supervision of 22 PhD Students (additional 2 international students), 2 post docs and more than 30 master and engineers students
  • Guest Editor for Special Issue Microprocessors and Microsystems Journal in 2014
  • Vice Chair of Electronic Design and Automation Association – EDAA
  • Vice Chair of European Test Technology Technical Council,  IEEE Computer Society Chapter
  • General Chair of MEDIAN Workshop 2015, IEEE ETS 2012, IEEE IOLTS 2005
  • Vice General Chair of IEEE VLSI Test Symposium 2017
  • Program General Chair of IEEE Nanoarch 2017, IEEE VTS 2015 and 2016, MEDIAN 2013, DCIS 2008 and 2009, DRVW 2008 and 2009.
  • Member of Program Committee of several IEEE international conferences and workshops related to design, test, reliability and fault tolerance : VTS, ETS, DATE, LATS, IOLTS, DTIS, IDT, ITC, DCIS, ISVLSI, NANOARCH, DFTS, DMTM, DRVW, EWME, ICCAD, PRIME, SELSE, MEDIAN

Cursus and Diploma

  • Septembre 2010, Full University Professor (61ème CNU) at Grenoble Institute of Technology, Grenoble (Grenoble INP), Physics, Electronics and Materials Engineering School, affiliated at TIMA Laboratory
  • Septembre 2007, Habilitation à Diriger des Recherches at Grenoble Institute of Technology, Grenoble (Grenoble INP), Micro and Nano Electronics Specialty
  • 2001-2010, Associate Professor (61 section CNU) at Grenoble Institute of Technology, Grenoble (Grenoble INP), Electronics and Telecommunication Engineering School, affiliated at TIMA Laboratory
  • 2000- 2001, Assistent Professor (27ème section CNU) at Joseph Fourier University, Applied Mathematics Institute, Grenoble
  • 2000, PhD in Microelectronic Design, at Grenoble Institute of Technology, Grenoble (Grenoble INP). Cum Laudae
  • 1997, Master of Science at Polytechnic University of Bucharest, Romania, Electronics and Telecommunication Engineering School
  • 1996, Engineer Degree in Electronics and Telecommunication  at Polytechnic University of Bucharest, Romania, Electronics and Telecommunication Engineering School