Teaching

During  2000-2015, I have been leading teaching activities in the following topics related to VLSI microelectronic design, System Level Design, and Computer Architectures:

  • Design and Test of Digital Circuits (18h lectures and 24h of Lab sessions) – Last year Engineering School – Master2 level
  • Fault Tolerant Hardware and Software Design ( 18h lectures) – Last year Engineering School – Master2 level
  • VLSI Design for ASIC and FPGA – basics (20h lectures, 22h lab session,   56h of Project) – Second year Engineering School – Master1 level
  • System On Chip Design – Embedded System Design (14h lectures, 20h lab sessions and 56h Project) – Last year Engineering School – Master2 level
  • Advanced VLSI Design – Low Power Design – 8h Lectures, Last year Engineering School – Master2 level
  • VHDL Hardware Description Language (8h Lectures and 12h lab sessions), First Year of Engineering School – Licence Level, and Second year Engineering School – Master1 level
  • Micro-controler and Microprocessor Architecture and Design, 18h lectures and Lab sessions, First Year of Engineering School – Licence Level

I also teach in Lifelong Training Curricula developed at Grenoble INP (Department de Formation Continue) in occasional and 3-years long teaching curricula – Manager Technique

  • Low power Design – 8h lectures
  • VLSI Digital Design and Test – 16h lectures
  • VLSI Design Flow – 20h lectures
  • VLSI Design for FPGA Implementation – 32h lectures and lab sessions
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